Napatech Link Programmable Software

Napatech Link Programmable Software

Link-Programmable™ Development Kit:

Interface cables necessary to program the hardware using a Xilinx Vivado^® Probe
A comprehensive hardware manual
Xilinx Vivado^® pinout files
Xilinx example design images (PCIe, QSFP, DDR)

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Napatech Link Programmable Software

Napatech Link Programmable Software – Engineered for High Performance Computing

Flagship tech specs

TECH SPECS	NT200A02 SmartNIC
Form factor	Half length, full height PCIe
Front ports	2 x QSFP28 front ports supporting 1, 10, 25, 40, 50, 100 GbE
FPGA	Xilinx Ultrascale+, XCVU5P-2FLGA2104E On demand: • XCVU7P-2FLVA2104E • XCVU9P-2FLVA2104E Optional: Speed Grade 1 or 3
Configuration flash	2 banks of 1 Gbit, 4 bit wide (QSPI)
Memory	3 x DDR4 banks of 64 bit @ 2666 Mbps, total: 12 GB Optional: 24 GB using 16 Gbit devices
PCIe	x16 Gen3 Optional: 2 x 8 Gen4 below PCIe spec v0.7 (1)
1000Base-T port	RJ45 front port connected to 1 Gb PHY with full SyncE and IEEE 1588v2 capabilities
Single ended coaxial I/O	Front port SMA connector and 2 internal MCX connectors
High-speed interconnect port	Interconnect bidirectional bandwidth of 675 Gb/s with Napatech interconnect cable Top: 2 x high-speed interconnect ports with 6 lanes each Optional: Back: 3 x high-speed interconnect ports; 2 with 6 lanes each and 1 with 4 lanes + SPI, 12V and clock
Power consumption	HW design: 120 W UL compliant with NIM to 75 W Idle: 5 W
Reference clock	20 MHz TCXO +/- 4.6 ppm Optional: 20 MHz OCXO +/- 0.01 ppm
Board microcontroller	ATxmega128A1U
Hardware board monitoring	Temperature and power sensors

(1) For detailed information regarding limitations on PCIe Gen4 support in Xilinx UltraScale+, please contact Xilinx.

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